AN EFFICIENT ARCHITECTURE FOR DE-BLOCKING FILTER

H.264 standard uses block based motion estimation, motion compensation, transform and quantization processes to perform video compression. By the use of block based operations, it would result into the discontinuity at block boundary-known as blocking artifacts. In this paper, high throughput filter architecture for real-time implementation of deblocking filter is presented which reduces memory access requirements and results in less clock cycles, to process a macroblock. Post processing approach is used in the paper in order to reduce the blocking artifacts and hence for reducing complexity of the architecture. The proposed architecture design uses only 23 clock cycles to process a single macroblock and in addition, the architecture effectively utilizes the buffers to store the intermediate data. The operational frequency of the proposed architecture is 55.675 MHz. The proposed architecture is implemented in VHDL and synthesize for Xilinx FPGA. It can process 75 HD frames with 1920x1080 resolutions.